From 4717a027cdd311b7b6def1a1ce9ed83e68ccddcc Mon Sep 17 00:00:00 2001
From: Nicola Sparnacci <nicola.sparnacci@seco.com>
Date: Tue, 19 Mar 2024 14:04:15 +0100
Subject: [PATCH] [C57][DTS][C57-30] Add CAN support
---
arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
index 69605ef36b1e8a..2ad1a0c5cf6615 100644
--- a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
+++ b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
@@ -52,6 +52,7 @@
serial4 = &cm40_lpuart;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
+ can0 = &flexcan1;
i2c1 = &i2c1;
i2c4 = &cm40_i2c;
i2c5 = &i2c0_mipi_lvds0;
@@ -410,6 +411,13 @@
IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000021
>;
};
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21
+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21
+ >;
+ };
pinctrl_qspi0: qspi0grp {
fsl,pins = <
@@ -856,6 +864,12 @@ gpio5: &lsio_gpio5 {
phy-reset-duration = <2>;
};
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi0>;
--
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