From 41e62b0411d84e3d92deac79b83b0bacca4b9a52 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Date: Mon, 16 Dec 2013 11:24:13 +0000 Subject: [PATCH] MIPS: asm: r4kcache: Build flushing code for instruction cache Build code to invalidate an address range in the instruction cache using the Hit Invalidate cache operation. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/r4kcache.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index c84caddb8bdede..789792eeb4f13e 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -456,6 +456,7 @@ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ protected_, loongson2_) __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) /* blast_inv_dcache_range */ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) -- GitLab