From 3b90cb39da9fd88c742a2392b06887a80ef105ba Mon Sep 17 00:00:00 2001
From: Leonard Crestez <leonard.crestez@nxp.com>
Date: Tue, 2 Apr 2019 15:39:15 +0300
Subject: [PATCH] MLK-21296 clk: imx8mm: Remove CLK_SET_RATE_GATE from
arm_a53_div
On recent kernels clks which are marked with CLK_SET_RATE_GATE are
"protected" against further changes at clk_prepare time. This
clk_core_rate_protect propagates up the clk tree and causes cpufreq
switches to fail later on.
See drivers/clk/clk.c around line 770.
Fix this by removing the CLK_SET_RATE_GATE flag for this specific clk.
This is safe because a53 clks are always only manipulated through
cpufreq.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
---
drivers/clk/imx/clk-imx8mm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 5709bfce578cc6..1af5814c8375f0 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -545,7 +545,8 @@ static void __init imx8mm_clocks_init(struct device_node *ccm_node)
clks[IMX8MM_CLK_GPU3D_CG] = imx_clk_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28);
clks[IMX8MM_CLK_GPU2D_CG] = imx_clk_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28);
- clks[IMX8MM_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+ clks[IMX8MM_CLK_A53_DIV] = imx_clk_divider_flags("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3,
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
clks[IMX8MM_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
clks[IMX8MM_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
clks[IMX8MM_CLK_GPU3D_DIV] = imx_clk_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3);
--
GitLab