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Commit 156021cd authored by Oleksii Kutuzov's avatar Oleksii Kutuzov
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[IMX8MM][MYON2][DTB] Add the standalone Myon 2 device tree 

Separated from the ConXM carrier board
parent 56116d24
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arch/arm64/boot/dts/seco/Makefile
+ 1
− 1
View file @ 156021cd
......@@ -11,7 +11,7 @@ dtb-$(CONFIG_ARCH_MXC) += seco-imx8mq-c12.dtb\
seco-imx8mp-d18.dtb\
seco-imx8qxp-c57.dtb\
seco-imx8mm-c72.dtb\
seco-imx8mm-myon2-conxm-hdmi.dtb\
seco-imx8mm-myon2.dtb
dts-dirs += overlays
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/seco/seco-imx8mm-myon2.dts 0 → 100644
+ 716
− 0
View file @ 156021cd
/*
* Copyright 2024-2025 SECO
*
*/
/dts-v1/;
#include "include/imx8mm.dtsi"
#include "include/myon2-pinfunc.h"
/ {
model = "SECO Myon II i.MX8MM module";
compatible = "kk,myon2","kk,trizeps8", "kk,trizeps8mini", "fsl,imx8mm-evk", "fsl,imx8mm";
chosen {
stdout-path = &uart1;
};
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rpmsg_reserved: rpmsg@b8000000 {
no-map;
reg = <0 0xb8000000 0 0x400000>;
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc1_vmmc: usdhc1_vmmc {
compatible = "regulator-fixed";
regulator-name = "VMMC_USDHC1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VMMC_USDHC2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
};
#if defined(MYON2_SWITCH_USDHC2_VQMMC) && (MYON2_SWITCH_USDHC2_VQMMC==1)
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
compatible = "regulator-gpio";
regulator-name = "VDDIO_USDHC2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd_vsel>;
gpios = <sd_vsel_gpio GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <1800000 1>, <3300000 0>;
};
#endif
sound: snd {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8983-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Speaker", "Speaker",
"Line","LineIn Jack",
"Microphone", "Microphone";
simple-audio-card,routing =
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"Headphone Jack", "OUT4",
"Speaker", "SPKL",
"Speaker", "SPKR",
"LineIn Jack", "L2",
"LineIn Jack", "R2",
"Microphone", "LIP",
"Microphone", "LIN",
"Microphone", "MICBIAS";
cpudai: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
};
simple-audio-card,codec {
sound-dai = <&audiocodec>;
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
sound-micfil {
compatible = "fsl,imx-audio-micfil";
model = "imx-audio-micfil";
cpu-dai = <&micfil>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 100000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
status = "disabled";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
/*
spidev0: spi@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
*/
};
&gpu {
status = "okay";
};
&i2c1 { /* CAM_I2C on J71-67,69 */
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 { /* I2C on Port4 J70-66,68 (typ. touch) */
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 { /* Internal I2C and Port6 J70-19,21 (typ. RTC) */
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pmic@4b {
compatible = "seco,bd71847";
reg = <0x4b>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 { // VDD_SOC_0V8
regulator-name = "BUCK1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 { // VDD_SOC_0V9
regulator-name = "BUCK2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 { // VDD_DRAM_PU_0V9
// BUCK5 in datasheet
regulator-name = "BUCK3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 { // +3V3_AUX
// BUCK6 in datasheet
regulator-name = "BUCK4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 { // VDD_1V8
// BUCK7 in datasheet
regulator-name = "BUCK5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 { // NVCC_DRAM_1V1
// BUCK8 in datasheet
regulator-name = "BUCK6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 { // NVCC_SNVS_1V8
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 { // VDD_SNVS_0V8
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 { // VDDA_1V8
regulator-name = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 { // VDD_PHY_0V9
regulator-name = "LDO4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: LDO5 { // VDD_ENET_2V5
regulator-name = "LDO5";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 { // VDD_PHY_1V2
regulator-name = "LDO6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
audiocodec: codec@1a { /* Audio-Codec */
compatible = "seco,wm8983";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
clock-names = "mclk";
};
mipi2lvds_bridge: sn65dsi83@2c {
status = "disabled";
compatible = "ti,sn65dsi83";
reg = <0x2c>;
enable-gpios =<lvds_en_gpio GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_enable>;
};
};
&lcdif {
status = "okay";
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MM_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
hard-wired = <1>;
ext_osc = <0>;
reserved-region = <&rpmsg_reserved>;
status = "disabled";
};
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "disabled";
};
&snvs_pwrkey {
status = "disabled";
};
&vpu_g1 {
status = "okay";
};
&vpu_g2 {
status = "okay";
};
&vpu_h1 {
status = "okay";
};
&vpu_v4l2 {
status = "okay";
};
&uart1 { /* UART on Port2 (debug) J70-69,71 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 { /* UART on Port1 J70-61,63 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart3 { /* UART on Port 3 J70-54,58 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "disabled";
};
/* usbmisc_imx.c Disable VBUS Comparator
PHY_CFG1:0x357371c5
PHY_CFG2:0x901cc020
*/
&usbotg1 {
dr_mode = "host";
extcon = <0>;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
/* disable-vbus-comparator = <1>; */
status = "disabled";
};
&usbotg2 {
dr_mode = "host";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "disabled";
};
&usdhc1 {
compatible = "fsl,imx8mm-usdhc";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
bus-width = <8>;
vmmc-supply = <&reg_usdhc1_vmmc>;
voltage-ranges = <3300 3300>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
pm-ignore-notify;
keep-power-in-suspend;
#if defined(MYON2_SWITCH_USDHC2_VQMMC) && (MYON2_SWITCH_USDHC2_VQMMC==1)
vqmmc-supply = <&reg_usdhc2_vqmmc>;
voltage-ranges = <1800 1800 3300 3300>;
#else
no-1-8-v;
voltage-ranges = <3300 3300>;
#endif
status = "disabled";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
>;
};
pinctrl_ecspi2_cs: ecspi2cs {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_lvds_enable: lvds_en_grp {
/* internal LVDS Enable and external Pin0-72 */
fsl,pins = <
PIN0_72_GPIO1_IO4 PAD_GPIO
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
/*
pinctrl_sd_vsel: sdvselgrp {
fsl,pins = <
SD_VSEL_GPIO PAD_GPIO
>;
};
*/
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x140 /* RTS */
MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x140 /* CTS */
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 /* SCHEMA/LAYOUT: RXD */
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 /* SCHEMA/LAYOUT: RTS */
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 /* SCHEMA/LAYOUT: TXD */
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 /* SCHEMA/LAYOUT: CTS */
>;
};
pinctrl_usdhc1_gpio: usdhc1grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
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