From 0bd25e0b6b72989d2b279ac6688b3c794f2701d5 Mon Sep 17 00:00:00 2001
From: Nicola Sparnacci <nicola.sparnacci@seco.com>
Date: Fri, 23 Feb 2024 09:26:05 +0100
Subject: [PATCH] [C57][DTS] Enable LVDS backlight
---
arch/arm64/boot/dts/seco/overlays/Makefile | 2 +
arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts | 343 ++++++++++++++----
2 files changed, 274 insertions(+), 71 deletions(-)
diff --git a/arch/arm64/boot/dts/seco/overlays/Makefile b/arch/arm64/boot/dts/seco/overlays/Makefile
index c2d4539af2d5fb..c60774ef37a3ef 100644
--- a/arch/arm64/boot/dts/seco/overlays/Makefile
+++ b/arch/arm64/boot/dts/seco/overlays/Makefile
@@ -51,6 +51,8 @@ dtbo-$(CONFIG_ARCH_MXC) += \
seco-imx8mn-c72-edp.dtbo\
seco-imx8mn-c72-lvds-dual-215.dtbo\
seco-imx8mn-c72-lvds-dual-156.dtbo
+ seco-imx8mn-c72-edp.dtbo \
+ seco-imx8qxp-c57-lvds-1024x600.dtbo
# seco-imx8qm-c26-dp.dtbo\
# seco-imx8qm-c26-lvds-single.dtbo\
diff --git a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
index 4fb20c7e4458db..c09007d2990529 100644
--- a/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
+++ b/arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts
@@ -29,13 +29,26 @@
};
aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ dsi_phy0 = &mipi0_dphy;
+ dsi_phy1 = &mipi1_dphy;
+ mipi_dsi0 = &mipi0_dsi_host;
+ mipi_dsi1 = &mipi1_dsi_host;
+ ldb0 = &ldb1;
+ ldb1 = &ldb2;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
mmc0 = &usdhc1;
- ethernet0 = &fec1;
- ethernet1 = &fec2;
+ i2c5 = &i2c0_mipi_lvds0;
+ i2c6 = &i2c0_mipi_lvds1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
};
cpus {
@@ -60,13 +73,142 @@
interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*cn15 connector*/
+ reg_en_bckl1_drv: en_bckl_drv {
+ status = "disabled";
+ compatible = "regulator-fixed";
+ regulator-name = "EN_BCKL_DRV";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ // startup-delay-us = <40000>;\
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ reg_backlight_vcc_bkl_sw: backlight_vcc_bkl_sw {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight_vcc_bkl_sw";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ //gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; /* This is configured by u-boot */
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_en_vcc_lcd: en_vcc_lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "EN_VCC_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_backlight_on: reg_backlight_on {
+ compatible = "regulator-fixed";
+ regulator-name = "BACKLIGHT_ON";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_lvds_panel_on: lvds_panel_on {
+ compatible = "regulator-fixed";
+ regulator-name = "LVDS_PANEL_ON";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ mux_sel: mux_sel {
+ compatible = "regulator-fixed";
+ regulator-name = "MUX_SEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+ };
+
+ /* Both Panels backlight + MP3385AGR */
+ lvds_backlight0 {
+ compatible = "mp3385-backlight";
+ pwms = <&pwm_mipi_lvds0 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <90>;
+ client-device = <&mp3385_led_driver>;
+ };
+
+ /* Backlight on CN25 (pin30) */
+ lvds_backlight1 {
+ compatible = "pwm-backlight";
+ pwms = <&pwm_mipi_lvds1 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <90>;
+ };
};
+
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
imx8qxp-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+
+ /*BACKLIGHT on - EN_VCC_BKL_SW*/
+ IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 0x00000021 /* bckl gpio RevB */
+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000021 /* bckl gpio RevC */
+ /*DISPLAY_BLK_ON*/
+ IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x00000021
+ /*LVDS PANEL ON*/
+ IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 0x00000021
+ /*MUX_SEL LVDS*/
+ IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000021
+ /*EN_BCKL_DRV*/
+ IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000021
+ /*EN_VCC_LCD_SW*/
+ IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000021
+ >;
+ };
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
@@ -89,6 +231,67 @@
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
>;
};
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
+ IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
+ IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
+ IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
+ IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
+ IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
+ IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
+ IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
+ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
+ /*RST ENET0 GPIO0_IO14*/
+ IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 0x00000021
+
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
+ IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
+ IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
+ IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
+ IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
+ IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
+ IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
+ IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
+ IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
+ IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
+ IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
+ /*RST ENET1 GPIO3_IO13*/
+ IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000021
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2cgrp {
+ fsl,pins = <
+ IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x0600004c
+ IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x0600004c
+ >;
+ };
+
+ pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020
+ >;
+ };
+
+ pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020
+ >;
+ };
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
@@ -137,51 +340,21 @@
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
- IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
- IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
- IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
- IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
- /*RST ENET0 GPIO0_IO14*/
- IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 0x00000021
-
- >;
- };
-
- pinctrl_fec2: fec2grp {
- fsl,pins = <
- IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
- IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
- IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
- IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
- IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
- IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
- IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
- IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
- IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
- IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
- IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
- IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
- /*RST ENET1 GPIO3_IO13*/
- IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000021
- >;
- };
+
};
};
+gpio0: &lsio_gpio0 {
+};
+gpio1: &lsio_gpio1 {
+};
+gpio2: &lsio_gpio2 {
+};
+gpio3: &lsio_gpio3 {
+};
+gpio4: &lsio_gpio4 {
+};
+
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@@ -201,29 +374,6 @@
status = "okay";
};
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&usb3_phy {
- status = "okay";
-};
-
-&usbotg3 {
- status = "okay";
-};
-
-&usbotg3_cdns3 {
- dr_mode = "host";
- status = "okay";
-};
-
&fec1 {
status = "okay";
pinctrl-names = "default";
@@ -232,10 +382,10 @@
phy-handle = <ðphy0>;
fsl,magic-packet;
- phy-reset-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
phy-reset-active-high;
- phy-reset-duration = <2>;
-
+ phy-reset-duration = <2>;
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -271,7 +421,58 @@
phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
fsl,magic-packet;
- phy-reset-gpios = <&lsio_gpio3 13 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
phy-reset-active-high;
phy-reset-duration = <2>;
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ mp3385_led_driver: mp3385@31 {
+ status = "okay";
+ compatible = "seco,led_mp3385";
+ reg = <0x31>;
+ reg-val = <0xf1 0xc4 0x3b 0x03 0x7f 0xe0 0x01>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&pwm_mipi_lvds0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>;
+ status = "okay";
+};
+
+&pwm_mipi_lvds1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>;
+ status = "okay";
};
\ No newline at end of file
--
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