From 09e62b162a5f1fbd60d72b1907e6f61667c89493 Mon Sep 17 00:00:00 2001
From: Jacky Bai <ping.bai@nxp.com>
Date: Mon, 18 Feb 2019 14:03:40 +0800
Subject: [PATCH] MLK-20951 arm: imx: Update the mmdc io save/restore on
imx7ulp
When system enters VLPS/VLLS mode, the IOMUXC config register
for MMDC related IO pads need to set to '0' to reduce the current
leakage for these IO pads.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/mach-imx/pm-imx7ulp.c | 24 +++++++++++++++++-------
arch/arm/mach-imx/suspend-imx7ulp.S | 16 ++++++++++++++--
2 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
index 41c7d391d7064b..238d36cd7d241e 100644
--- a/arch/arm/mach-imx/pm-imx7ulp.c
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -86,7 +86,7 @@
#define BP_PMCTRL_STOPM 0
#define BP_PMCTRL_PSTOPO 16
-#define MX7ULP_MAX_MMDC_IO_NUM 36
+#define MX7ULP_MAX_MMDC_IO_NUM 64
#define MX7ULP_MAX_MMDC_NUM 50
#define MX7ULP_MAX_IOMUX_NUM 116
#define MX7ULP_MAX_SELECT_INPUT_NUM 78
@@ -190,12 +190,22 @@ struct imx7ulp_pm_socdata {
};
static const u32 imx7ulp_mmdc_io_lpddr3_offset[] __initconst = {
- 0x128, 0xf8, 0xd8, 0x108,
- 0x104, 0x124, 0x80, 0x84,
- 0x88, 0x8c, 0x120, 0x10c,
- 0x110, 0x114, 0x118, 0x90,
- 0x94, 0x98, 0x9c, 0xe0,
- 0xe4,
+ 0x0, 0x4, 0x8, 0xc,
+ 0x10, 0x14, 0x18, 0x1c,
+ 0x20, 0x24, 0x28, 0x2c,
+ 0x30, 0x34, 0x38, 0x3c,
+ 0x40, 0x44, 0x48, 0x4c,
+ 0x50, 0x54, 0x58, 0x5c,
+ 0x60, 0x64, 0x68, 0x6c,
+ 0x70, 0x74, 0x78, 0x7c,
+ 0x80, 0x84, 0x88, 0x8c,
+ 0x90, 0x94, 0x98, 0x9c,
+ 0xa0, 0xa4, 0xa8, 0xac,
+ 0xb0, 0xb4, 0xb8, 0xbc,
+ 0xc0, 0xc4, 0xc8, 0xcc,
+ 0xd0, 0xd4, 0xd8, 0xdc,
+ 0xe8, 0xf8, 0xfc, 0x120,
+ 0x124,
};
static const u32 imx7ulp_mmdc_lpddr3_offset[] __initconst = {
diff --git a/arch/arm/mach-imx/suspend-imx7ulp.S b/arch/arm/mach-imx/suspend-imx7ulp.S
index b3e0317d5070bb..6e11c1c46c811b 100644
--- a/arch/arm/mach-imx/suspend-imx7ulp.S
+++ b/arch/arm/mach-imx/suspend-imx7ulp.S
@@ -60,8 +60,8 @@
#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a4
#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a8
/* below offsets depends on MX7ULP_MAX_MMDC_IO_NUM(36) definition */
-#define PM_INFO_MMDC_NUM_OFFSET 0x4c8
-#define PM_INFO_MMDC_VAL_OFFSET 0x4cc
+#define PM_INFO_MMDC_NUM_OFFSET 0x5a8
+#define PM_INFO_MMDC_VAL_OFFSET 0x5ac
#define DGO_CTRL0 0x50
#define DGO_GPR3 0x60
@@ -331,6 +331,18 @@ poll_dvfs_set:
ands r7, r7, #(1 << 24)
beq poll_dvfs_set
+ /* put mmdc io into lpm */
+ ldr r11, [r0, #PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET]
+ ldr r10, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+ ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
+ add r7, r7, r0
+mmdc_io_lpm:
+ ldr r8, [r7], #0x8
+ mov r9, #0x0
+ str r9, [r11, r8]
+ subs r10, r10, #0x1
+ bne mmdc_io_lpm
+
/* switch NIC clock to FIRC */
ldr r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET]
ldr r7, [r10, #SCG_NICCCR]
--
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